1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. More particularly, embodiments of the invention relate to an output buffer circuit for a semiconductor memory device.
This application claims priority to Korean Patent Application No. 10-2005-32827, filed on Apr. 20, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor memory devices are well known and widely used to store and retrieve data. There are many different kinds of semiconductor memory devices, but they may be generally classified as random access memory (RAM) and a read only memory (ROM). A RAM device is a volatile memory device that loses stored data when power is interrupted. A ROM device is a nonvolatile memory device that holds stored data in spite of an interruption in power. RAM devices include dynamic RAM devices and static RAM devices. ROM devices include programmable ROM devices, erasable RPOM devices, electrically erasable/programmable EPROM devices, and flash memory devices.
Regardless of their specific design, semiconductor memory devices include a plurality of output buffer circuits. An output buffer circuit generally receives a plurality of input signals, and thereafter, simultaneously outputs a plurality of corresponding output signals during an output mode of operation. Figure (FIG.) 1 is a block diagram illustration of a conventional plurality of output buffer circuits.
Referring to FIG. 1, sixteen (16) output buffer circuits, including 100_1, . . . , 100_N−1, 100_N, 100_N+1, and, 100_16 are illustrated. Each of these output buffer circuits respectively receives input signals DIN_1, . . . , DIN_N−1, DIN_N, DIN_N+1, DIN_16, and correspondingly outputs output signals DOUT_1, . . . , DOUT_N−1, DOUT_N, DOUT_N+1, . . . , DOUT_16. In the illustrated example, it is assumed that each of output buffer circuits has essentially the same structure and performs essentially identical operations. As one more detailed example, output buffer circuit 100_N is formed from an inverter including a P-MOS transistor PT11 and an NMOS transistor NT11. Output buffer circuit 100_N is adapted to receive the input signal DIN_N and output a corresponding output signal DOUT_N.
FIG. 2 shows a typical waveform for output signal DOUT_N provided by output buffer circuit 100_N of FIG. 1.
Referring to FIG. 2, the waveform is formed by dividing the output signal continuously provided from the output buffer circuit by one cycle and combining the divided output signals. Waveform A is formed by combining the divided high level output signals, and waveform B is formed by combining the divided low level output signals. Waveform A is provided when the input signal is low and waveform B is provided when the input signal is high. In this context, the terms “high” and “low” refer to arbitrarily defined, alternate logic or signal states, as is common in the art.
As shown in FIG. 2, the output buffer circuit provides a somewhat distorted output signal due to an accumulation of signal noise. Noise often arises when the input signal applied to DIN_N is low, but an adjacent input signal (e.g., one applied to DIN_N+1 and/or DIN_N−1) is high. Noise may also arise when the input signal applied to DIN_N is high, but an adjacent signal (e.g., one applied to DIN_N+1 and/or DIN_N−1) is low. At extreme levels, adjacent channel induced noise (or cross-talk) may make the output signal provided by the output buffer circuit unintelligible. Thus, there exists a continuing demand for an output buffer circuit providing output signals with reduced noise, despite the presence of different signal levels on adjacent signal lines.